Frequency synthesizers are widely used in communications systems to generate signals with desired operating frequencies. FIG. 1 is a block diagram of a frequency synthesizer embodiment. An input signal with a stable frequency is sent to a programmable reference frequency divider 105 to produce a reference frequency, fref. The reference frequency is sent to a phase frequency detector (PFD) 115.
The synthesizer output is generated by a voltage controlled oscillator (VCO) 140 that oscillates at a desired frequency. The VCO's output, fout, is controlled by a phase locked loop in which a dual modulus prescaler 130 provides a feedback signal, fb, based on the VCO output. PFD 115 compares fb and fref, and adjusts its output according to the difference. The output of the PFD is sent to charge pump 120 for generating a control voltage. The control voltage is filtered by loop filter 125, and then sent to VCO 140 for generating a desired output, fout. The frequency of fout can be changed by varying the frequency of fref or the frequency of fb. Thus, the frequency synthesizer is able to generate different channel frequencies needed by the system.
Dual modulus prescaler 130 includes P and S counters 135 and divider 145. The divider modulus is selected from two integer constants, usually denoted as N and N+1. The output of the VCO, fout, is divided by the selected modulus to generate a clock signal. S and P counters 135 use the clock to count up to a fixed value S′ and a fixed value P′, respectively. The counters control the selection of N and N+1, determine the frequency of fb, and indirectly determine the frequency of fout.
Typically, P′ defines the frequency band of the output and S′ defines the channels within the bands. It is sometimes useful to decrease the minimum S′ so the synthesizer can generate more channels with narrower channel spacing in-between. Sometimes, however, there is a tradeoff between the number of channels generated and the minimum output frequency. As the number of channels increases, so does the minimum output frequency. The resulting minimum output frequency may not meet system requirements. The problem cannot be simply solved by decreasing the reference frequency since a lower reference frequency adversely affects the performance of the synthesizer. It would be useful to have a frequency synthesizer design that would mitigate the tradeoff problem, allowing more channels to be generated and keeping the minimum output frequency low. It would also be desirable if the reference frequency can be increased without reducing the number of channels that can be generated.